1. Field of the Invention
The present invention relates to semiconductor devices having PLL circuits, and particularly to a semiconductor device which requires controlling a delay time of an output signal of the PLL circuit.
2. Description of the Background Art
In order to increase the margins of a setup time of data input to an LSI and a hold time of the data output, a clock signal inside the LSI (an internal clock signal) is phase-adjusted with respect to a clock signal inputted from the outside of the LSI (an external clock signal.) For external data, as shown in FIG. 15, the setup time is the time t set from the point at which external data is prepared to the point at which the external data is captured inside (to the rising edge of the internal clock signal in FIG. 15.) For internal data, it corresponds to the time t set from the point at which internal data is prepared to the point at which the internal data is outputted to the outside (to the rising edge of the internal clock signal in FIG. 15.) The hold time is, concerning external data, the time t hold in which the external data is continuously kept ready after captured inside, as shown in FIG. 15. Concerning internal data, it corresponds to the time t hold in which the internal data is continuously kept ready after outputted to the outside. The phase-locked loop circuit (PLL circuit) is suitable for the adjustment of the internal clock signal.
FIG. 10 is a block diagram showing a conventional semiconductor device. In FIG. 10, 1 denotes an input terminal for inputting an external clock signal with a cycle CL, 2 denotes an output terminal for outputting an internal clock signal, 6 denotes a phase detector , 7 denotes a loop filter for filtering an output of the phase detector 6, 8 denotes a voltage-controlled oscillator, 11 denotes a delay circuit, 4 denotes one input terminal of the phase detector 6 for inputting a signal from the delay circuit 11, 5 denotes the other input terminal of the phase detector 6 for inputting a signal from the voltage-controlled oscillator 8, 10 denotes an output terminal of the voltage-controlled oscillator 8, and 16 denotes an input terminal of the voltage-controlled oscillator 8.
Next, the structure of the semiconductor device shown in FIG. 10 will be described. The delay circuit 11 has its input connected to the input terminal 1 and its output connected to the input terminal 4. The output of the phase detector 6 is connected to the input of the loop filter 7. The output of the loop filter 7 is connected to the input terminal 16. The output terminal 10 is connected to the output terminal 2 and to the input terminal 5. The phase detector 6, the loop filter 7 and the voltage-controlled oscillator 8 form a PLL circuit.
FIG. 11 is a circuit diagram showing the internal configuration of the voltage-controlled oscillator 8. In FIG. 11, 8b denotes an inverting amplifier, 8a denotes a control portion for controlling the inverting amplifiers 8b according to a signal at the input terminal 16, INV denotes an inverter, and other characters correspond to those in FIG. 10. Next, the configuration of the voltage-controlled oscillator 8 will be described. The plurality of inverting amplifiers 8b are connected in a loop to form a ring oscillator. An output of one of the plurality of inverting amplifiers 8b is connected to the output terminal 10 through the inverter INV. The control portion 8a has its input connected to the input terminal 16 and its output connected to each inverting amplifier 8b.
FIG. 12 is a circuit diagram showing an example of internal configuration of the delay circuit 11. In FIG. 12, INV denotes an inverter, R denotes a resistance, C denotes a capacitance and other characters correspond to those in FIG. 10. A delay circuit having multistage-connected inverters to utilize delays between inputs and outputs of the inverters may be used instead of that shown in FIG. 12.
Next, operation of the semiconductor device shown in FIG. 10 will be described. FIG. 13 is a timing chart showing the relation between an external clock signal at the input terminal 1 and an internal clock signal at the output terminal 2. The PLL circuit operates so that the phase of the signal at the input terminal 4 and that of the internal clock signal at the output terminal 2 coincide with each other. The delay circuit 11 receives the external clock signal at the input terminal 1 to provide a signal delayed by a delay time td2 with respect to the external clock signal to the input terminal 4. Accordingly, the internal clock signal at the output terminal 2 is delayed in phase by the delay time td2 behind the external clock signal at the input terminal 1. In other words, the phase of the internal clock signal at the output terminal 2 is apparently more advanced than that of the external clock signal at the input terminal 1 by a delay time td1 (=the cycle of the external clock signal -the delay time td2.)
The conventional semiconductor device having the PLL constructed as stated above have the problems given below.
First, when the delay time is realized with the delay circuit 11 including the capacitance C and the resistance R, a larger layout area is required for the capacitance C and the resistance R as a larger delay time is required. When it is realized with a delay circuit utilizing delays of inverters, then the number of inverters INV increases to increase the layout area.
Furthermore, since the capacitance value of the capacitance C and the resistance value of the resistance R and the like are affected by process, the delay time may differ with different processes. Even with the same process, the delay time may differ because of different finish states caused by different conditions.
Moreover, for example, consider the case in which an LSI containing the semiconductor device shown in FIG. 10 is installed in a system such as a board and an external clock signal is supplied from the system. The delay circuit 11 is designed considering the cycle of the external clock signal. If there are a plurality of systems with external clock signals having different cycles, a delay circuit 11 must be designed for each system. Thus it introduces the problem that the delay circuit 11 must be designed according to the cycle of the external clock signal.
Furthermore, since the delay time is one fixed value, it is impossible to deal with various setup times and hold times. For example, consider that the PLL circuit shown in FIG. 10 is contained in an LSI to output internal data generated inside the LSI in synchronization with the internal clock signal and capture external data generated outside the LSI in synchronization with the internal clock signal. Referring to FIG. 15, the time t hold and the time t set can be changed by setting the delay time in the delay circuit 11 in the designing step to change the delay time of the internal clock signal. However, if the time t hold in capturing external data is lengthened by changing the delay time of the internal clock, the time t set in outputting internal data becomes shorter. On the other hand, if the time t set in capturing external data is lengthened, the time t hold in outputting internal data becomes shorter. This way, the setup time and the hold time are in a trade-off relation. Hence, changing one of the setup time and the hold time causes the other to change. Thus the setup time and the hold time can not be independently adjusted.